1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device that is suitable for a pulse-triggered flip-flop circuit.
2. Description of Related Art
Flip-flop circuits are widely used in integrated circuits such as LSIs. Flip-flop circuits include synchronous type circuits and non-synchronous type circuits. In a synchronous type flip-flop circuit an output is changed synchronously with a clock signal input. Synchronous type flip-flop circuits include various types of circuits such as a master-slave flip-flop circuit and a pulse-triggered flip-flop circuit.
A pulse-triggered flip-flop circuit is a circuit that changes an output only in a narrow-width pulse period that is synchronized with a clock signal input. Since a setup time and a delay time in this kind of pulse-triggered flip-flop are small, recently pulse-triggered flip-flops are often used in high-end processors.
Pulse-triggered flip-flops include an HLFF (Hybrid Latch F/F), an SDFF (Semi-dynamic F/F), a CCFF (Conditional Capture F/F), and a DMFF (Data Mapping F/F) as respectively described in the following literature:
Partovi, H., et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements,” in ISSCC Dig. Tech. Papers, February 1996, pp. 138-139 (hereunder referred to as “Document 1”);
Klass, F., “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 108-109 (hereunder, referred to as “Document 2”); and
B.-S. Kong, S.-S Kim, Y.-H. Jun, “Conditional-Capture Flip-Flop for Statistical Power Reduction,” IEEE J. Solid-State Circuits, vol. 36, pp. 1263-1271, August 2001 (hereunder referred to as “Document 3”).
With a pulse-triggered flip-flop it is necessary to define a narrow-width pulse period that is synchronized with a clock signal input as the internal timing, and it is also necessary to secure a timing width that has some margin with respect to fluctuations in PVT (process, power supply voltage, temperature) conditions.
This kind of internal timing interval, that is, internal timing width, can be obtained using an inverter that delays a clock signal input. A required delay amount can be obtained according to the number of inverters that are connected in cascade. More specifically, in the case of pulse-triggered flip-flops, a sufficient number of inverters are necessary in order to secure the required internal timing width. Consequently, when including pulse-triggered flip-flops in an integrated circuit, the problem is that the area occupied by the flip-flops in the integrated circuit increases.